The demand for greater circuit density and higher performance in Complementary Metal Oxide Semiconductor (CMOS) transistors is driving the critical gate dimension to 65 nm and below. For MOS-based IC manufacturing, a polysilicon gate has been used for many generations in spite of some shortcomings that include the well known poly-depletion effect which was first recognized over 10 years ago. The continued miniaturization of MOS Field Effect Transistor (MOSFET) devices and associated demand for better channel electrostatic control, higher gate capacitance, and higher drive current means that the gate dielectric thickness needs to be scaled down aggressively. For the 65 nm technology node and beyond, the equivalent electrical gate oxide thickness (EOT) must be thinned to below 15 Angstroms. Since poly-depletion has consistently contributed 4 to 10 Angstroms to the total EOT, the poly-depletion effect is no longer acceptable, regardless of advancements made on the high k dielectric layer between the gate and channel. To reduce the high gate resistance and poly-depletion problems, the active dopant density in the polysilicon gate must be increased. However, this practice leads to carrier mobility degradation. Thus, a considerable amount of research and development effort is taking place to identify an alternative gate electrode such as a metal electrode that is much more conductive than conventional heavily doped polysilicon gates and is free of the poly-depletion issue.
Many types of metal electrodes and associated schemes have been investigated. Examples of conductive materials used in metal gate technology are metals such as W and Mo, metal silicides including nickel silicide and cobalt silicide, and metallic nitrides such as TiN and WN. An important requirement for a gate electrode is its capability of having a tunable work function (Φm) around its mid-gap so that the threshold voltage (Vth) for NMOS and PMOS devices can be obtained symmetrically. One attractive approach for implementing a metal gate in a transistor device is to employ a silicidation process that completely consumes a conventional polysilicon gate electrode which is converted to a silicide. A metal gate formed through the process of silicidation and referred to as a Fully Silicided (FUSI) poly gate is a strong contender for gate electrode in advanced technologies because an n-type or p-type dopant that is implanted into polysilicon can modulate the final Φm around the ΦMid-Gap such as in pure nickel silicide without dopant. In other words, a semiconductor has a certain energy level measured by its Fermi level or EF. An undoped semiconductor has an EF generally at the middle of the bandgap. N-type doping adjusts the EF closer to the conduction band while p-type doping moves the EF nearer the valence band.
There are several examples of FUSI poly gates but the methodology with regard to assembling all processes effectively seems lacking. Moreover, a better design is needed to overcome some performance issues and to enable a lower cost manufacturing process that involves fewer steps.
A recent improvement in the design of transistor devices involves raised source and drain regions which increases the thickness of the source and drain regions available for the silicidation process and lowers sheet resistance of the source and drain regions. An example of elevated source/drain regions that are coplanar with a metal gate electrode is found in U.S. Pat. No. 6,284,609 in which a doped epitaxial growth serves as a raised source/drain region. A metal gate is enclosed on the sides and bottom by oxide liners and a gate dielectric layer, respectively. However, selective epitaxial growth (SEG) requires a separate tool set and the process itself is not easy to perform, thereby increasing manufacturing expense. Additionally, gate formation requires removing a dielectric layer above the channel by an etch process which could damage the substrate below the subsequently formed gate.
In U.S. Pat. No. 6,204,103, a transistor device having fully silicided polysilicon gates and silicided S/D regions is disclosed. One drawback is that the gates and S/D regions are silicided in separate steps that could have different thermal budget allowances and thereby lead to thermal instability and an increase in S/D resistance. Secondly, the gate and S/D regions are not coplanar which could lead to complications during a subsequent etch step that opens contact holes to silicided regions. Moreover, separate masks are required for patterning two different metal layers on the respective gates.
U.S. Pat. No. 5,960,270 describes a MOS transistor in which a metal gate is deposited in an opening above the channel region after silicided S/D regions are formed in the substrate. However, damage to the gate region could easily occur during etching to remove a sacrificial gate. Since the gate region is the most critical portion of a transistor, a gate replacement scheme as disclosed here is questionable in terms of process margin.
U.S. Patent Application 2004/0094804 and a related publication entitled “Issues in NiSi-gated FDSOI device integration”, J. Kedzierski, et al., IEDM, 2003, describe fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates. While this approach appears to more closely resemble a full integration flow than other prior art examples, the fabrication still has the disadvantages of separate S/D and gate silicidations, SEG to raise the S/D regions, and non-planar gate and raised S/D regions.
In silicon-on-insulator (SOI) technology, the source/drain regions are formed above an insulator layer, allowing a significant reduction in the source and drain depletion capacitance. On the other hand, for a thin body SOI case, a high series resistance associated with fully silicided source and drain regions and due to the significantly reduced side contact areas, must be overcome before SOI technology is implemented in manufacturing.
In summary, there are several obstacles to implementing fully silicided gates and S/D regions in CMOS technology. Current process flows are too complex and incur extra cost because S/D and gate silicidation occur separately. Note that a gate has a greater thickness than S/D regions which require thinner silicide to avoid S/D junction leakage. Typically, a second (gate) silicidation demands a higher temperature and longer time than S/D silicidation to avoid non-uniform NiSi (phase) formation that causes Φm variability. A high thermal budget for the gate silicidation could affect the pre-formed S/D silicide (often NiSi as well) with a resulting Rs increase from silicide agglomeration. When a SEG process is implemented to raise the S/D region, an extra tool and more process time are needed. Even so, the SEG thickness is limited and cannot achieve a level that is coplanar with the gate. Subjecting a thick gate and a thinner raised S/D region to a single silicidation process will likely cause S/D junction damage. A fourth issue is non-planarity of silicided gate and S/D regions as mentioned previously. A fifth concern is that a SEG raised S/D thickness is limited and even a silicided SEG raised S/D region is not thick enough to separate a subsequently formed Cu contact in a BEOL process flow from an active S/D with sufficient distance.